Some microprocessors and/or processor cores (referred to generically herein as “processors”) may include or otherwise have access to a primary cache memory, such as a level one (“L1”) cache, or other memory structure from which the processor may retrieve frequently accessed information, such as data or instructions, relatively quickly in relation to other memory structures in the processor or computing system. In addition, some processors may include or otherwise have access to a secondary cache memory, such as a level two (“L2”) cache memory, or other memory structure from which it may retrieve less frequently accessed information, such as data or instructions, less quickly than from a primary cache memory but faster than from a system memory, such as dynamic random access memory (DRAM), hard-drive memory, etc.
Some computer systems may include processors, each including or otherwise having access to a local cache memory, such as an L1 cache, to store information that is to be primarily used by the processor to which it corresponds. Furthermore, some computer systems may include a shared cache memory, such as an L2 cache, that may be used by more than one processor. In computer systems having shared cache memory, the shared cache memory may store all or some portion of information stored in each of the local cache memories, such that multiple local cache memories store a subset of frequently used information stored in the shared cache memory. Information stored in local cache memories may be updated more frequently than the corresponding information in the shared cache memory, and therefore, the computer system may implement a cache coherency scheme to maintain the same information in the shared cache memory as is stored in one or more local cache memories.
Some computer systems may use power management techniques to place processors in the system in low power modes, via reducing clock frequency and/or voltage to one or more processors in the system, when a particular processor isn't being used or in response to other algorithms, such as those in which temperature of the processor or computer system is monitored and prevented from exceeding a threshold temperature. Processors that are placed in low power modes may retain information stored in their corresponding local cache memory while in the low power mode by, for example, maintaining power to the local cache, such that the information will be available when the processor returns from the low power mode.
One drawback of prior art techniques of retaining cached information during a low power mode is that processors that may access a cache of a processor in a low power mode, via a “snoop” cycle, for example, may have to wait until the processor in the low power mode returns from the low power mode and can respond to the access by the other processor. The latency between the access to the low power mode processor's cache and when the requested data is either retrieved or determined not to exist in the low power mode processor's cache can significantly diminish the performance of the corresponding computer system. The problem may be exacerbated when the number of processors are increased, as the number of processors that may be in a low power mode and the number of accesses to these processors may increase. Furthermore, the computer system may draw unnecessary power, particularly if the requested information is determined not to exist in the local cache of the processor that's in a low power mode.